The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2016

Filed:

Feb. 28, 2015
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Inventors:

Hiromasa Yoshimori, Kanagawa, JP;

Hirofumi Tokita, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/266 (2006.01); H01L 29/66 (2006.01); H01L 27/115 (2006.01); H01L 21/28 (2006.01); H01L 29/792 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/266 (2013.01); H01L 21/28282 (2013.01); H01L 21/82345 (2013.01); H01L 21/823468 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 29/66545 (2013.01); H01L 29/66833 (2013.01); H01L 29/7833 (2013.01); H01L 29/792 (2013.01); H01L 21/823462 (2013.01); H01L 29/6659 (2013.01);
Abstract

Provided is a semiconductor device having improved performance. Over a semiconductor substrate, a dummy control gate electrode is formed via a first insulating film. Over the semiconductor substrate, a memory gate electrode for a memory cell is formed via a second insulating film having an internal charge storage portion so as to be adjacent to the dummy control gate electrode. At this time, the height of the memory gate electrode is adjusted to be lower than the height of the dummy control gate electrode. Then, a third insulating film is formed so as to cover the dummy control gate electrode and the memory gate electrode. Then, the third insulating film is polished to expose the dummy control gate electrode. At this time, the memory gate electrode is not exposed. Then, the dummy control gate electrode is removed and replaced with a metal gate electrode.


Find Patent Forward Citations

Yoshimori, Hiromasa. (2016). Method of manufacturing semiconductor device (U.S. Patent No. 9460929). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9460929

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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