The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 2016
Filed:
Mar. 04, 2015
Vayavya Labs Private. Limited, Belgaum, IN;
Srivatsan Raghavan, Bengaluru, IN;
Karthick Gururaj, Bengaluru, IN;
Sandeep Pendharkar, Bengaluru, IN;
Someshwar DK, Bengaluru, IN;
Shrinivas Nagaraddi, Bengaluru, IN;
Other;
Abstract
A computer-implemented verification system for performing a system level or a system on chip level functional verification of integrated circuit is provided. The computer-implemented system includes one or more processors and a memory storing instructions defined by one or more modules of including a scenario compiler, a verification component and a software library component. The scenario compiler receives a set of verification scenario intents including at least one of test-application intents, constraints, device-programming intents and scenario-control intents. The scenario compiler generates one or more open verification methodology (OVM) and/or universal verification methodology (UVM) compliant test bench sequences and one or more scenario software implementations based on the set of verification scenario intents. The verification component interacts with the integrated circuit using the OVM and/or UVM compliant test bench sequences. The software library component enables execution of the scenario software implementations on a processing unit core of the integrated circuit.