The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2016

Filed:

Feb. 20, 2013
Applicant:

Hannstar Display Corp., New Taipei, TW;

Inventors:

Chun-Chin Tseng, Kaohsiung, TW;

Ya-Wen Lee, Tainan, TW;

Kuo-Wen Pan, Kaohsiung, TW;

Assignee:

HANNSTAR DISPLAY CORP, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G02F 1/133 (2006.01); H03K 17/16 (2006.01); G09G 5/18 (2006.01); G11C 19/28 (2006.01); G09G 5/00 (2006.01);
U.S. Cl.
CPC ...
G02F 1/13306 (2013.01); G09G 3/3677 (2013.01); G09G 5/18 (2013.01); G11C 19/28 (2013.01); H03K 17/16 (2013.01); H03K 17/161 (2013.01); G09G 5/008 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01); G09G 2370/08 (2013.01);
Abstract

An integrated gate driver circuit includes a control circuit, a plurality of drive stages and a plurality of discharge transistors. The control circuit is configured to output a plurality of clock signals within a frame period and to output a discharge enabling signal within a blanking period of the frame period. Each of the drive stages receives the clock signals and includes an output terminal configured to output a gate driving signal. Each of the discharge transistors is coupled to the output terminal of one of the drive stages and discharges the output terminal according to the discharge enabling signal thereby eliminating the voltage fluctuation of the output terminal in the blanking period.


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