The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 27, 2016
Filed:
Dec. 31, 2014
Texas Instruments Incorporated, Dallas, TX (US);
Divyasree J., Bangalore, IN;
Anant Shankar Kamath, Plano, TX (US);
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Abstract
An FLL (frequency locked loop) oscillator/clock generator includes a free-running oscillator (such as a ring oscillator), and generates an FLL_clk with an FLL-controlled frequency f. The FLL control loop includes a switched capacitor resistor divider that converts fto a resistance, generating an FLL feedback voltage Vfosc used to generate a loop control signal OSC_cntrl input to the oscillator. In response, the oscillator frequency locks FLL_clk to fosc. In an example implementation, the FLL oscillator/clock operates with spread spectrum clocking (SSC) that provides triangular SSC modulation based on a truncated RC transition voltage generated as a negative feedback to an RC relaxation oscillator, with truncation based on switched tripping threshold voltages generated a positive feedback to the RC relaxation oscillator.