The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 27, 2016
Filed:
Oct. 17, 2014
Applicants:
Gaurav Goyal, Greater Noida, IN;
Ashis Maitra, New Delhi, IN;
Ateet Mishra, Delhi, IN;
Inventors:
Assignee:
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/3562 (2006.01); H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
H03K 3/35625 (2013.01); H03K 19/1737 (2013.01);
Abstract
Flip-flop cells that enable time borrowing during the design of the IC to improve setup times while avoiding introducing meta-stability, and alternatively to avoid hold time violations. The flip-flop cells are connected with logic cells in functional data paths. The flip-flop cell has a clock signal controlling both its input and output. A selective delay cell selectively delays either a data signal input to the flip-flop cell or the clock signal controlling the flip-flop cell. The selectively delayed signal adjusts the timing (setup, hold and clock-to-output) of the data path.