The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2016

Filed:

Dec. 17, 2013
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Ning Cheng, Cupertino, CA (US);

Huaqiang Wu, Burlingame, CA (US);

Hiro Kinoshita, Sunnyvale, CA (US);

Jihwan Choi, San Mateo, CA (US);

Angela Hui, Milpitas, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 29/792 (2006.01); G11C 16/34 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 29/792 (2013.01); G11C 16/3427 (2013.01); H01L 27/11565 (2013.01); H01L 27/11568 (2013.01); H01L 29/1083 (2013.01); H01L 29/66833 (2013.01); H01L 29/7923 (2013.01); H01L 21/26586 (2013.01);
Abstract

Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.


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