The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2016

Filed:

Jul. 27, 2015
Applicant:

Samsung Display Co., Ltd., Yongin, KR;

Inventors:

Je Hun Lee, Seoul, KR;

Jun Ho Song, Seongnam-si, KR;

Yun Jong Yeo, Seoul, KR;

Hwa Dong Jung, Seoul, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 29/40 (2006.01); H01L 21/28 (2006.01); H01L 21/268 (2006.01); H01L 21/308 (2006.01); H01L 21/02 (2006.01); H01L 29/423 (2006.01); H01L 29/86 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66742 (2013.01); H01L 21/02205 (2013.01); H01L 21/2686 (2013.01); H01L 21/28247 (2013.01); H01L 21/3086 (2013.01); H01L 27/1214 (2013.01); H01L 29/0847 (2013.01); H01L 29/401 (2013.01); H01L 29/42356 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78693 (2013.01); H01L 29/86 (2013.01);
Abstract

A thin film transistor array panel includes a substrate, a light blocking film disposed on the substrate, a buffer layer covering the light blocking film, and a channel region disposed on the buffer layer. A source region and a drain region are disposed in the same layer as the channel region. A gate insulating layer is disposed on the channel region, and a gate electrode overlaps the channel region, with the gate insulating layer interposed between the gate electrode and the channel region. A passivation layer is disposed on the gate electrode, the source region, the drain region, and the buffer layer. A source electrode and a drain electrode are disposed on the passivation layer, wherein the channel region, the source region, and the drain region comprise an oxide semiconductor, and wherein a carrier concentration of the source region and the drain region is larger than in the channel region.


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