The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2016

Filed:

Nov. 27, 2013
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Zhanfeng Cao, Beijing, CN;

Qi Yao, Beijing, CN;

Luke Ding, Beijing, CN;

Bing Sun, Beijing, CN;

Xiangchun Kong, Beijing, CN;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 27/12 (2006.01); H01L 29/51 (2006.01); G02F 1/1368 (2006.01); H01L 29/49 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42364 (2013.01); G02F 1/1368 (2013.01); H01L 27/124 (2013.01); H01L 27/1225 (2013.01); H01L 29/4908 (2013.01); H01L 29/517 (2013.01); H01L 29/7869 (2013.01); H01L 29/78606 (2013.01); H01L 2029/42388 (2013.01);
Abstract

The present invention provides a thin film transistor and a method of fabricating the thin film transistor, an array substrate and a method of fabricating the array substrate, and a display device. The thin film transistor includes a substrate and a gate, an insulation layer, an active layer, a source and a drain which are provided on the substrate. A spacer layer is also provided between the gate and the active layer, and the spacer layer overlaps at least with one of the gate and the active layer having a smaller area in an orthographic projection direction. The spacer layer can effectively prevent material forming the gate from being diffused into the active layer, thereby ensuring stability of performance of the thin film transistor. In the array substrate utilizing the thin film transistor, the spacer layer further extends to a region corresponding to a gate line.


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