The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2016

Filed:

Mar. 31, 2015
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

JianHua Ju, Shanghai, CN;

Shuai Zhang, Shanghai, CN;

Shaofeng Yu, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/0217 (2013.01); H01L 21/3081 (2013.01); H01L 21/3086 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 21/823493 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 21/823892 (2013.01); H01L 27/0924 (2013.01);
Abstract

A method of manufacturing a fin-type field effect transistor includes sequentially forming a first mask and a second mask on a semiconductor substrate; patterning the second mask; forming and patterning a third mask on the second mask in accordance with a fin pattern of the fin-type field effect transistor; etching the semiconductor substrate, the first mask, and the second mask through the third mask, wherein portions of the first and second masks are removed and a first trench is formed in the semiconductor substrate; removing the third mask; etching the first mask through the second mask and removing the second mask; etching the semiconductor substrate through the first mask to form a plurality of fins and a second trench disposed between adjacent fins, wherein etching the semiconductor substrate further deepens the first trench such that a depth of the first trench is greater than a depth of the second trench.


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