The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2016

Filed:

Dec. 23, 2013
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Inventors:

Jumpei Konno, Kanagawa, JP;

Takafumi Nishita, Kanagawa, JP;

Nobuhiro Kinoshita, Kanagawa, JP;

Kazunori Hasegawa, Kanagawa, JP;

Michiaki Sugiyama, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/488 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 24/81 (2013.01); H01L 23/49838 (2013.01); H01L 24/13 (2013.01); H01L 24/14 (2013.01); H01L 24/16 (2013.01); H01L 24/743 (2013.01); H01L 24/97 (2013.01); H01L 21/561 (2013.01); H01L 21/563 (2013.01); H01L 23/49816 (2013.01); H01L 23/49894 (2013.01); H01L 2224/10175 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81193 (2013.01); H01L 2224/81801 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/92125 (2013.01); H01L 2924/0132 (2013.01); H01L 2924/0133 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/15184 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01);
Abstract

Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member.


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