The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 27, 2016
Filed:
Apr. 07, 2014
Applicant:
SK Hynix Inc., Icheon, KR;
Inventor:
Seung Jee Kim, Seongnam, KR;
Assignee:
SK HYNIX INC., Icheon, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 23/13 (2006.01);
U.S. Cl.
CPC ...
H01L 24/11 (2013.01); H01L 23/13 (2013.01); H01L 24/19 (2013.01); H01L 25/0657 (2013.01); H01L 24/06 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/06155 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/131 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73217 (2013.01); H01L 2924/12042 (2013.01);
Abstract
An embedded package includes a core layer having a cavity, a first semiconductor chip disposed in the cavity, and bumps disposed on a top surface of the first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip and the core layer, pads disposed on a top surface of the second semiconductor chip, and a first insulation layer disposed on the core layer and the first and second semiconductor chips. The first insulation layer has first openings that expose the bumps and second openings that expose the pads, and the first and second openings have a similar depth.