The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2016

Filed:

Jan. 11, 2016
Applicants:

International Business Machines Corporation, Armonk, NY (US);

Global Foundries Inc, Grand Cayman, KY (US);

Inventors:

Takashi Ando, Tuckahoe, NY (US);

Changhwan Choi, Seoul, KR;

Kisik Choi, Watervliet, NY (US);

Vijay Narayanan, New York, NY (US);

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/161 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823842 (2013.01); H01L 21/02178 (2013.01); H01L 21/02192 (2013.01); H01L 21/28079 (2013.01); H01L 21/28088 (2013.01); H01L 21/28229 (2013.01); H01L 21/823807 (2013.01); H01L 21/823857 (2013.01); H01L 29/1054 (2013.01); H01L 29/161 (2013.01); H01L 29/495 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01);
Abstract

A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a PMOS region. A dummy gate structure may be formed over the high-k dielectric and etched to form an opening over the NMOS region and an opening over the PMOS region. Thereafter, first work function metals are deposited in the NMOS opening and second work function metals are applied in the PMOS openings. A suitable gate electrode material may then fill the remainder of the NMOS and PMOS openings.


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