The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2016

Filed:

Mar. 23, 2015
Applicant:

Marvell Israel (M.i.s.l) Ltd., Yokneam, IL;

Inventors:

Carol Pincu, Rison Leziyon, IL;

Ido Bourstein, Karkur, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/82 (2006.01); H01L 25/065 (2006.01); H01L 21/822 (2006.01); H01L 23/12 (2006.01); H01L 23/498 (2006.01); H01L 23/544 (2006.01); H01L 23/14 (2006.01); H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/78 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82 (2013.01); H01L 21/4857 (2013.01); H01L 21/78 (2013.01); H01L 21/8221 (2013.01); H01L 23/12 (2013.01); H01L 23/147 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/5385 (2013.01); H01L 23/544 (2013.01); H01L 25/0655 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/157 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01);
Abstract

Systems and methods are provided for an interposer for coupling two or more integrated circuit dies to a circuit package. A first integrated circuit portion is disposed on a first location of a single semiconductor substrate. A second integrated circuit portion is disposed on a second location of the single semiconductor substrate, where the second integrated circuit portion is electrically isolated from the first integrated circuit portion along a first axis. The first and second integrated circuit portions are configured to provide an electrical coupling to two or more corresponding top die integrated circuits across a second axis that is perpendicular to the first axis.


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