The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 27, 2016
Filed:
Nov. 25, 2014
Applicant:
SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;
Inventor:
Han Soo Joo, Chungcheongbuk-do, KR;
Assignee:
SK hynix Inc., Icheon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 7/00 (2006.01); G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01); H01L 29/792 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
G11C 7/00 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/3427 (2013.01); H01L 27/11582 (2013.01); H01L 29/7926 (2013.01); G11C 16/107 (2013.01);
Abstract
A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array including cell strings coupled between bit lines and a common source line, each of the cell strings comprising a plurality of memory cells stacked above a substrate. The semiconductor memory device also includes a peripheral circuit configured to supply a negative voltage to one or more word lines coupled to the cell strings and supply a positive voltage to the common source line, wherein the peripheral circuit supplies the positive voltage and the negative voltage before a program operation is performed.