The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2016

Filed:

Feb. 25, 2015
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventor:

Kazuaki Oishi, Yokohama, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/45 (2006.01); H03F 1/02 (2006.01);
U.S. Cl.
CPC ...
H03F 3/45179 (2013.01); H03F 1/0211 (2013.01); H03F 1/0272 (2013.01); H03F 3/45085 (2013.01); H03F 3/45197 (2013.01); H03F 3/45659 (2013.01); H03F 3/45748 (2013.01); H03F 2200/144 (2013.01); H03F 2203/45118 (2013.01); H03F 2203/45418 (2013.01); H03F 2203/45434 (2013.01); H03F 2203/45481 (2013.01); H03F 2203/45512 (2013.01); H03F 2203/45526 (2013.01); H03F 2203/45528 (2013.01); H03F 2203/45631 (2013.01); H03F 2203/45694 (2013.01); H03F 2203/45702 (2013.01);
Abstract

A differential amplification circuit includes: a first input node; a second input node; a first output node; a second output node; a first transistor having a gate coupled to the first input node and a source coupled to a first node; a second transistor having a gate coupled to the second input node; a third transistor having a drain coupled to a drain of the first transistor; a fourth transistor having a gate coupled to a gate of the third transistor; a first resistor; a second resistor; a fifth transistor having a gate coupled to the drain of the first transistor; a sixth transistor having a gate coupled to the drain of the second transistor; a seventh transistor having a source coupled to the first node; an eighth transistor having a gate coupled to a gate of the seventh transistor; a third resistor; and a fourth resistor.


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