The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2016
Filed:
May. 28, 2013
Altera Corporation, San Jose, CA (US);
Cheng-Hsiung Huang, Cupertino, CA (US);
Kyle Bowers, Morgan Hill, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Integrated circuits with electrostatic discharge (ESD) protection circuitry are provided. Integrated circuits may include input-output pins that are coupled to the ESD protection circuitry. The ESD protection circuitry may include diode circuits, a control circuit, and a power clamp circuit. Each diode circuit may have a first terminal that is coupled to a respective input-output pin and a second terminal that is coupled to a shared ESD control line. The control circuit may supply a boosted voltage onto the control line to reverse bias the diode circuits during normal operation while the power clamp is turned off. During an ESD event, the power clamp may be turned on to sink current from the diode circuits. The power clamp may include a transistor having a substrate that is forward biased to improve transistor drive strength during the ESD event and that is reverse biased to reduce leakage during normal operation.