The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2016

Filed:

Jul. 31, 2015
Applicant:

Seoul Semiconductor Co., Ltd., Ansan-si, KR;

Inventors:

Jung Hwa Jung, Ansan-si, KR;

Jung Doo Kim, Ansan-si, KR;

Seoung Ho Jung, Ansan-si, KR;

Min Hye Kim, Ansan-si, KR;

Yoo Jin Kim, Ansan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 33/50 (2010.01); H01L 33/48 (2010.01); H01L 33/62 (2010.01); H01L 33/46 (2010.01); H01L 25/075 (2006.01);
U.S. Cl.
CPC ...
H01L 33/50 (2013.01); H01L 33/486 (2013.01); H01L 33/62 (2013.01); H01L 25/0753 (2013.01); H01L 33/46 (2013.01); H01L 33/505 (2013.01); H01L 33/508 (2013.01); H01L 2224/48091 (2013.01); H01L 2924/181 (2013.01);
Abstract

Disclosed is a light emitting device having a wavelength converting layer. The light emitting device comprises a plurality of semiconductor stacked structures; connectors for electrically connecting the plurality of semiconductor stacked structures to one another; a single wavelength converting layer for covering the plurality of semiconductor stacked structures; an electrode electrically connected to at least one of the semiconductor stacked structures; and at least one additional electrode positioned on the electrode, passing through the wavelength converting layer to be exposed to the outside, and forming a current input terminal to the light emitting device or a current output terminal from the light emitting device. Since the single wavelength converting layer covers the plurality of semiconductor stacked structures, the plurality of semiconductor stacked structures can be integrally mounted on a chip mounting member such as a package or a module.


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