The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2016

Filed:

Oct. 10, 2013
Applicant:

Texas State University, San Marcos, TX (US);

Inventors:

In-Hyouk Song, San Marcos, TX (US);

Byoung Hee You, San Marcos, TX (US);

Heung Seok Kang, Daejeon, KR;

Kang-Hee Lee, Daejeon, KR;

Assignee:

Texas State University, San Marcos, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
H01L 29/515 (2013.01); H01L 29/42372 (2013.01); H01L 29/51 (2013.01); H01L 29/66477 (2013.01); H01L 29/78 (2013.01); H01L 29/7841 (2013.01);
Abstract

Methods for forming a vertically movable gate field effect transistor (VMGFET) on a silicon-on-insulator (SOI) wafer are described. The methods include providing a process of making VMGFET devices without critical alignment of masks between sequential etch and diffusion steps. The oxide layer of the SOI wafer is used for a self-limiting etch stop layer and for a sacrificial layer to form an insulating layer between a gate electrode and a substrate. The proper location of the gate electrode with respect to the source and drain junctions is insured by using a silicon gate structure as a mask layer for the diffusion process for defining the source and drain junctions.


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