The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2016

Filed:

Jul. 20, 2013
Applicants:

Young Jin Choi, Santa Clara, CA (US);

Jrjyan Jerry Chen, Campbell, CA (US);

Beom Soo Park, San Jose, CA (US);

Soo Young Choi, Fremont, CA (US);

Inventors:

Young Jin Choi, Santa Clara, CA (US);

Jrjyan Jerry Chen, Campbell, CA (US);

Beom Soo Park, San Jose, CA (US);

Soo Young Choi, Fremont, CA (US);

Assignee:

APPLIED MATERIALS, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); C23C 16/30 (2006.01); H01L 51/00 (2006.01); H01L 51/52 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02107 (2013.01); C23C 16/308 (2013.01); H01L 51/0096 (2013.01); H01L 51/5253 (2013.01); Y02E 10/549 (2013.01);
Abstract

The present disclosure describes methods of an interface adhesion improvement methods used on a transparent substrate for OLED or thin film transistor applications. In one embodiment, a method of forming a buffer layer on a surface of a substrate includes providing a substrate having an planarization material disposed thereon in a processing chamber, supplying a buffer layer gas mixture including a silicon containing gas into the processing chamber, controlling a substrate temperature less than about 100 degrees Celsius, forming a buffer layer on the planarization material, supplying an encapsulating barrier layer deposition gas mixture including a silicon containing gas and a nitrogen containing gas into the processing chamber, and forming an encapsulating barrier layer on the buffer layer.


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