The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2016

Filed:

Jun. 20, 2014
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Alan Jeremy Becker, Cambridge, GB;

Chiloda Ashan Senerath Pathirane, Cambridge, GB;

Robert Campbell Aitken, San Jose, CA (US);

Assignee:

ARM Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/14 (2006.01); G06F 11/00 (2006.01); G11C 29/16 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 29/14 (2013.01); G06F 11/008 (2013.01); G11C 29/16 (2013.01); G11C 2029/0409 (2013.01);
Abstract

A data processing apparatus has at least one memory and processing circuitry. A memory built-in self-test (MBIST) interface receives a MBIST request indicating that a test procedure is to be performed for testing at least one target memory location. Control circuitry detects the MBIST request and reserves for testing at least one reserved memory location including the target memory location. During the test procedure, the memory continues servicing memory transactions issued by the processing circuitry that target a memory location other than the reserved location reserved by the control circuitry. The processing circuitry is stalled if it attempts to access a reserved memory location. Testing consists of short bursts of transactions which occur infrequently. In this way, MBIST testing may continue while the processor is operation in the field with reduced performance impact.


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