The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2016

Filed:

Jun. 19, 2014
Applicant:

Phison Electronics Corp., Miaoli, TW;

Inventors:

Jen-Chu Wu, New Taipei, TW;

An-Chung Chen, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); H03L 7/091 (2006.01); H03L 7/08 (2006.01); H03L 7/081 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/22 (2013.01); G11C 7/1093 (2013.01); H03L 7/0805 (2013.01); H03L 7/0812 (2013.01);
Abstract

A sampling circuit module, a memory control circuit unit, and a method for sampling data are provided. The sampling circuit module includes a state machine circuit, a first delay line circuit, a second delay line circuit and a delay signal output circuit. In response to a first control signal, the state machine circuit outputs a second control signal and/or a third control signal. The first delay line circuit is configured to receive a reference clock signal and the second control signal to output a first delay clock signal. The second delay line circuit is configured to receive the reference clock signal and the third control signal to output a second delay clock signal. The delay signal output circuit is configured to receive the first delay clock signal and the second delay clock signal to output a third delay clock signal.


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