The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2016

Filed:

Apr. 06, 2015
Applicant:

Marvell International Ltd., Hamilton, BM;

Inventors:

Fei Sun, Santa Clara, CA (US);

Chang Shu, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/00 (2006.01); G06F 21/72 (2013.01); G06F 7/72 (2006.01); H04L 9/30 (2006.01);
U.S. Cl.
CPC ...
G06F 21/72 (2013.01); G06F 7/725 (2013.01); H04L 9/3066 (2013.01);
Abstract

A system including a first circuit and a second circuit. The first circuit includes a multiplier array to receive a first operand and a second operand and generate a plurality of outputs, an adder array to receive the plurality of outputs and generate a partial product of the first operand and the second operand including partial sums and carry bits, which are stored in a plurality of register arrays. The second circuit generates the product of the first operand and the second operand by implementing a two-stage reduction of the partial product of the first operand and the second operand. A first stage includes rearranging the partial sums and carry bits as two multi-bit integers. A second stage includes generating a plurality of multi-bit integers based on the two multi-bit integers, and generating the product of the first operand and the second operand based on the plurality of multi-bit integers.


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