The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2016
Filed:
Jun. 25, 2015
International Business Machines Corporation, Armonk, NY (US);
Roger Moussalli, Peekskill, NY (US);
Sameh Asaad, Briarcliff Manor, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for dynamically reconfiguring logic circuits on an FPGA includes the steps of: classifying a general function into sets of static functions and modal functions to be implemented on the FPGA; for each of the modal functions, generating a list of one-active actions; devising a circuit topology including at least a subset of look-up tables (LUTs) such that any one of the modal functions can be implemented at a time on the devised circuit topology; for each modal function, associating the devised circuit topology with a controller adapted to load a LUT configuration corresponding to a prescribed one of the one-active actions; implementing a single fixed circuit on the FPGA including devised circuit topologies for each of the modal functions; and updating contents of LUTs corresponding to the LUT configuration in the devised circuit topology when a change in modal function to be implemented on the FPGA is required.