The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2016
Filed:
Jun. 02, 2014
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Guoling Han, Fremont, CA (US);
Stephen A. Neuendorffer, San Jose, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5045 (2013.01); G06F 8/433 (2013.01); G06F 8/45 (2013.01); G06F 8/452 (2013.01); G06F 8/456 (2013.01); G06F 17/505 (2013.01); G06F 17/5054 (2013.01); G06F 2217/86 (2013.01);
Abstract
Extracting a system architecture in high level synthesis includes determining a first function of a high level programming language description and a second function contained within a control flow construct of the high level programming description. The second function is determined to be a data consuming function of the first function. Within a circuit design, a port including a local memory is automatically generated. The port couples a first circuit block implementation of the first function to a second circuit block implementation of the second function within the circuit design.