The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2016
Filed:
Apr. 01, 2015
Ateet Mishra, Delhi, IN;
Shiva Belwal, Nainital, IN;
Deepak Mahajan, Noida, IN;
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Abstract
An EDA tool for verifying timing constraints of an integrated circuit (IC) design includes a processor and a memory that stores register transfer level (RTL) code of the IC design and a timing constraint file. The processor generates a netlist based on the RTL code, and identifies asynchronous clock paths, false paths and multi-cycle paths in the netlist using the timing constraint file. The processor then inserts buffer cells for logic cells in the netlist. The processor also inserts buffer cells in the asynchronous clock paths, false paths, and multi-cycle paths. The processor delay annotates logic cells and clock delay cells with a zero delay value and the buffer cells with known delay values. The processor generates a modeled standard delay format (SDF) file and performs a gate level simulation (GLS) using the modeled SDF file.