The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2016

Filed:

Feb. 25, 2015
Applicant:

Broadcom Corporation, Irvine, CA (US);

Inventors:

Veronica Alarcon, San Jose, CA (US);

Walid Nabhane, Long Valley, NJ (US);

Mark Norman Fullerton, Austin, TX (US);

Love Kothari, Sunnyvale, CA (US);

Ronak Subhas Patel, Sunnyvale, CA (US);

Chih-Tsung Hsieh, Taipei, TW;

Hao-zheng Lee, Taipei, TW;

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 11/10 (2006.01); G05F 1/625 (2006.01); G06F 13/12 (2006.01); G06F 1/26 (2006.01); G01R 31/36 (2006.01); H02J 7/00 (2006.01); G06F 1/32 (2006.01); G11C 7/10 (2006.01); G06F 11/30 (2006.01); G01R 31/40 (2014.01); G01R 19/00 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1048 (2013.01); G01R 31/36 (2013.01); G05F 1/625 (2013.01); G06F 1/26 (2013.01); G06F 1/3206 (2013.01); G06F 1/3287 (2013.01); G06F 11/1016 (2013.01); G06F 11/3062 (2013.01); G06F 11/3093 (2013.01); G06F 13/126 (2013.01); G11C 7/106 (2013.01); G11C 7/1072 (2013.01); H02J 7/0029 (2013.01); G01R 19/003 (2013.01); G01R 31/40 (2013.01); G06F 11/3031 (2013.01); G06F 11/3058 (2013.01); Y02B 60/1282 (2013.01);
Abstract

A method for serial interface clock domain crossing includes identifying a data communication command received over a serial interface. An address is decoded to determine whether the address falls within a direct latch address range of a register bank. Data is communicated over the serial interface. A multiplexed output clock is generated, for writing to and reading from the register bank, based on at least one of a current system operating state and a refresh control signal from a host processor.


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