The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2016

Filed:

Oct. 03, 2013
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Ziyad S. Hakura, Gilroy, CA (US);

Cynthia Ann Edgeworth Allison, Madison, AL (US);

Dale L. Kirkland, Madison, AL (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 5/36 (2006.01); G06F 9/38 (2006.01); G06T 15/00 (2011.01); G06T 15/40 (2011.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01); G09G 5/395 (2006.01); G09G 5/00 (2006.01); G06T 15/50 (2011.01); G06F 12/08 (2016.01); G06F 9/44 (2006.01); G06T 15/80 (2011.01);
U.S. Cl.
CPC ...
G06F 9/38 (2013.01); G06F 9/44 (2013.01); G06F 12/0808 (2013.01); G06F 12/0875 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06T 15/005 (2013.01); G06T 15/405 (2013.01); G06T 15/503 (2013.01); G06T 15/80 (2013.01); G09G 5/003 (2013.01); G09G 5/395 (2013.01); G06F 2212/302 (2013.01); Y02B 60/1225 (2013.01);
Abstract

One embodiment of the present invention sets forth a technique for managing buffer entries in a tile-based architecture. The technique includes receiving a first plurality of graphics primitives and a first buffer address at which attributes associated with the first plurality of graphics primitives are stored. The technique further includes, for each tile included in a plurality of tiles, transmitting the first plurality of graphics primitives and the first buffer address to a screen space pipeline and receiving an acknowledgement from the screen space pipeline indicating that processing the first plurality of graphics primitives has completed. The technique further includes determining that processing the first plurality of graphics primitives has completed for a last tile included in the plurality of tiles and that the acknowledgement has been received for each tile included in the plurality of tiles, and, in response, releasing a buffer entry associated with the first buffer address.


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