The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2016

Filed:

Jul. 25, 2011
Applicants:

Andrew Marshall, Kanata, CA;

Henry Wong, Ottawa, CA;

Essaid Bensoudane, Ottawa, CA;

Inventors:

Andrew Marshall, Kanata, CA;

Henry Wong, Ottawa, CA;

Essaid Bensoudane, Ottawa, CA;

Assignee:

Semtech Canada Corporation, Burlington, Ontario, unknown;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/033 (2006.01); H04L 7/00 (2006.01); H03L 7/08 (2006.01); H04L 25/20 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0331 (2013.01); H03L 7/0807 (2013.01); H04L 7/0025 (2013.01); H04L 7/033 (2013.01); H04L 7/005 (2013.01); H04L 25/20 (2013.01);
Abstract

A circuit for reducing jitter in a digital signal is provided, comprising a clock and data recovery stage operative to receive an input data signal and generate in response thereto a recovered data signal, a recovered clock signal, and an unfiltered interpolator code; a filter stage operative to receive the unfiltered interpolator code and generate in response thereto a filtered clock signal; and a memory component operative to receive the recovered data signal, the recovered clock signal, and the filtered clock signal; sample the recovered data signal using the recovered clock signal; store the resulting sampled bits; and generate an output data signal by selecting stored bits using the filtered clock signal.


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