The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2016

Filed:

Feb. 20, 2015
Applicant:

Marvell World Trade Ltd., St. Michael, BB;

Inventors:

Poh Boon Leong, Cupertino, CA (US);

Albert Wu, Palo Alto, CA (US);

Long-Ching Wang, Cupertino, CA (US);

Sehat Sutardja, Los Altos Hills, CA (US);

Assignee:

MARVELL WORLD TRADE LTD., St. Michael, BB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/38 (2015.01); H04B 1/40 (2015.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/495 (2006.01); H01L 23/66 (2006.01); H01L 23/00 (2006.01); H01L 25/16 (2006.01); H01L 25/00 (2006.01); H04B 1/00 (2006.01); H04B 15/04 (2006.01); H01L 23/64 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H04B 1/40 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/49503 (2013.01); H01L 23/49575 (2013.01); H01L 23/66 (2013.01); H01L 24/17 (2013.01); H01L 24/49 (2013.01); H01L 24/85 (2013.01); H01L 25/16 (2013.01); H01L 25/162 (2013.01); H01L 25/50 (2013.01); H04B 1/00 (2013.01); H04B 15/04 (2013.01); H01L 23/645 (2013.01); H01L 28/10 (2013.01); H01L 2223/6644 (2013.01); H01L 2223/6672 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16265 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32265 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/49 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/85 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/102 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/1304 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1421 (2013.01); H01L 2924/19011 (2013.01); H01L 2924/19103 (2013.01);
Abstract

A circuit including a first die, an integrated passive device and a second layer. The first die includes a first substrate and active devices. The integrated passive device includes a first layer, a second substrate and passive devices. The second substrate includes vias. The passive devices are implemented at least on the first layer or the second substrate. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The second layer is disposed between the first die and the integrated passive device. The second layer includes pillars. Each of the pillars connects a corresponding one of the active devices to (i) one of the vias, or (ii) one of the passive devices. The first die, the integrated passive device and the second layer are disposed relative to each other to form a stack.


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