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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9443905 B1

PDFFull Text
Expired
Date of Patent:
Sep. 13, 2016

Filed:

Aug. 25, 2015

Implementing 3d scalable magnetic memory with interlayer dielectric stack and pillar holes having programmable area

Applicant:

Hgst Netherlands B.v., Amsterdam, NL;

Inventors:

Zvonimir Z. Bandic, San Jose, CA (US);

Jeffery Robinson Childress, San Jose, CA (US);

Luiz M. Franca-Neto, Sunnyvale, CA (US);

Jordan Asher Katine, Mountaine View, CA (US);

Neil Leslie Robertson, Palo Alto, CA (US);

Assignee:

HGST Netherlands B.V., Amsterdam, NL;

Attorney:

Joan Pennington

Primary Examiner:

David Lam

Int. Cl.
CPC ...
G11C 11/00 (2006.01); H01L 27/22 (2006.01); H01L 43/12 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); H01L 43/02 (2006.01); H01L 43/08 (2006.01); H01L 21/28 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
H01L 27/222 (2013.01); G11C 16/04 (2013.01); G11C 16/10 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01); H01L 43/12 (2013.01); G11C 11/16 (2013.01); H01L 21/28026 (2013.01);
Abstract

A three-dimensional (3D) scalable magnetic memory array and a method for implementing the three-dimensional (3D) scalable magnetic memory array for use in Solid-State Drives (SSDs) are provided. A three-dimensional (3D) scalable magnetic memory array includes an interlayer dielectric (IDL) stack of word planes separated by a respective IDL. A plurality of pillar holes is formed in the IDL stack in a single etch step; each of the pillar holes including an oxide barrier coating, and a first conductor M, and a second conductor Mforming magnetic pillar memory cells. The first conductor Mis formed of a magnetic material, and the second conductor Mis more electrically conductive than the conductor M; and each of the magnetic pillar memory cell inside the pillar holes have a programmable area using unpatterned programmable magnetic media proximate to a respective one of the word planes.

Find Patent Forward Citations

Bandic, Zvonimir. (2016). Implementing 3d scalable magnetic memory with interlayer dielectric stack and pillar holes having programmable area (U.S. Patent No. 9443905). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9443905

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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