The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2016

Filed:

Apr. 29, 2015
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventor:

Shingo Ohsaki, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01); H01L 21/3213 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/02164 (2013.01); H01L 21/02208 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/28 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 21/311 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/321 (2013.01); H01L 21/3212 (2013.01); H01L 21/3213 (2013.01); H01L 21/32115 (2013.01); H01L 21/32133 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01);
Abstract

A method of fabricating a memory device includes forming a mask over a top surface of a stack of alternating insulating material layers and control gate electrodes located over a substrate, wherein the stack has a memory opening extending vertically through the stack, a semiconductor channel extends vertically in the memory opening, and a memory film is located in the memory opening between the semiconductor channel and the plurality of control gate electrodes, and the mask covers a first portion of an upper insulating layer of the stack and exposes a second portion of the upper insulating layer adjacent to the memory opening, etching the upper insulating layer through the mask to provide a recess in the second portion of the upper insulating layer, and forming a conductive material within the recess to provide a select gate electrode adjacent to the semiconductor channel in the memory opening.


Find Patent Forward Citations

Loading…