The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2016
Filed:
Jul. 14, 2014
Avago Technologies General Ip (Singapore) Pte. Ltd., Singapore, SG;
Detlef Bernd Krabe, Munich, DE;
Martin Weigert, Etterzhausen/Bavaria, DE;
Avago Technologies General IP (Singapore) Pte. Ltd., Singapore, SG;
Abstract
Embedded Wafer-Level Packaging (eWLP) methods and optoelectronic devices, packages and assemblies made by the eWLP methods are described. The eWLP methods allow electrical interconnections to be easily and economically made to the back sides of the chips of the eWLP wafer using eWLP wafer-level processes, thereby eliminating the need to use TMVs or TSVs to make such interconnections. The eWLP methods also allow thermal and optical interconnections between the back side and the front side of the eWLP wafer to be easily and economically made. In addition, the eWLP methods allow electrical and optical interfaces to be formed on the front side and/or on the back side of the eWLP wafer. The eWLP methods may be used to form a variety of very thin optoelectronic devices, packages and assemblies having a various useful configurations with high volume, yield and throughput.