The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2016
Filed:
Jan. 15, 2010
Tony Vanhoucke, Bierbeek, BE;
Anco Heringa, Waalre, NL;
Johannes Josephus Theodorus Martinus Donkers, Valkenswaard, NL;
Jan Willem Slotboom, Eersel, NL;
Tony Vanhoucke, Bierbeek, BE;
Anco Heringa, Waalre, NL;
Johannes Josephus Theodorus Martinus Donkers, Valkenswaard, NL;
Jan Willem Slotboom, Eersel, NL;
NXP B.V., Eindhoven, NL;
Abstract
Disclosed is a method of manufacturing a vertical bipolar transistor in a CMOS process, comprising implanting an impurity of a first type into a the substrate () to form a buried region () therein; forming a halo implant () using an impurity of a second type and a shallow implant () using an impurity of the first type, said halo implant enveloping the shallow implant in the substrate and being located over said buried region (); forming, adjacent to the halo implant (), a further implant () using an impurity of the second type for providing a conductive connection to the halo implant; and providing respective connections () to the further implant (), the shallow implant () and the buried region () allowing the shallow implant, halo implant and buried region to be respectively operable as emitter, base and collector of the vertical bipolar transistor. Hence, an IC may be provided that comprises vertical bipolar transistors manufactured using CMOS processing steps only.