The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2016
Filed:
Nov. 29, 2013
Applicant:
Kabushiki Kaisha Toshiba, Minato-ku, JP;
Inventors:
Kenji Sakaue, Yokohama, JP;
Edward Bandy Samigat, Yokohama, JP;
Atsushi Takayama, Yokohama, JP;
Yutaka Tango, Yokohama, JP;
Assignee:
Kabushiki Kaisha Toshiba, Minato-ku, JP;
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); G11C 16/32 (2006.01); G06F 13/16 (2006.01); G11C 7/10 (2006.01); H03M 13/09 (2006.01); H03M 13/15 (2006.01);
U.S. Cl.
CPC ...
G11C 16/32 (2013.01); G06F 13/1689 (2013.01); G11C 7/106 (2013.01); G11C 7/1066 (2013.01); H03M 13/09 (2013.01); H03M 13/152 (2013.01); H03M 13/1515 (2013.01);
Abstract
According to one embodiment, a storage device includes a storage medium, a DLL circuit, a latch circuit, and a delay amount adjustment circuit. The DLL circuit gives a predetermined amount of delay to an inputted clock signal, the latch circuit latches data outputted from the storage medium in accordance with the clock signal delayed in the DLL circuit, the delay amount adjustment circuit adjusts the delay amount that the DLL circuit is to give to the clock signal based on a latch result by the latch circuit.