The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2016

Filed:

Aug. 19, 2014
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventors:

Moon-Ki Jung, Seoul, KR;

Ki-Won Lim, Suwon-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 7/14 (2006.01); G11C 29/02 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0002 (2013.01); G11C 7/14 (2013.01); G11C 13/004 (2013.01); G11C 29/021 (2013.01); G11C 29/026 (2013.01); G11C 29/028 (2013.01); G11C 29/50008 (2013.01); G11C 2013/0054 (2013.01); G11C 2213/71 (2013.01); G11C 2213/72 (2013.01);
Abstract

A method for testing a nonvolatile memory device includes: monitoring a first resistance dispersion and a second resistance dispersion of a nonvolatile memory device, determining a lower test bias level and an upper test bias level that are disposed on opposite sides of a reference bias level, calculating the number of first fail bits generated in the first resistance dispersion based on the lower test bias level and the number of second fail bits generated in the second resistance dispersion based on the upper test bias level, determining a selected reference bias level using the number of the first fail bits and the number of the second fail bits, and trimming the reference bias level to the selected bias level.


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