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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9443581 B1

PDFFull Text
Date of Patent:
Sep. 13, 2016

Filed:

Mar. 14, 2014

Electronic device and method for fabricating the same

Applicant:

SK Hynix Inc., Icheon-Si, KR;

Inventor:

Hyun-Jeong Kim, Icheon-Si, KR;

Assignee:

SK hynix Inc., Icheon-Si, KR;

Attorney:

Perkins Coie LLP

Primary Examiner:

Huan Hoang

Assistant Examiner:

Jay Radke

Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 13/02 (2006.01); G11C 13/00 (2006.01); H01L 45/00 (2006.01); H01L 27/22 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0002 (2013.01); G11C 13/003 (2013.01); H01L 27/228 (2013.01); H01L 27/2454 (2013.01); H01L 45/04 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); H01L 45/141 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01); G11C 2213/74 (2013.01); G11C 2213/79 (2013.01);
Abstract

An electronic device includes a semiconductor memory, the semiconductor memory including: a substrate configured to comprise a plurality of line patterns which are extended in a second direction, and a plurality of pillar patterns which protrude perpendicular to the line patterns and are arranged in the second direction and in a first direction crossing the second direction; a source line configured to be formed between the line patterns, to be coupled to the line patterns disposed at both sides of the source line, and to be extended in the second direction; a word line configured to be in contact with sidewalls of the pillar patterns arranged in the first direction, and to be extended in the first direction; an interconnection line configured to be disposed over the pillar patterns, and to be extended in the first direction so as to be coupled to the pillar patterns arranged in the first direction; variable resistance elements configured to be disposed over the interconnection line, and to be positioned between the pillar patterns which are adjacent to each other in the first direction; and a bit line configured to be disposed over the variable resistance elements, and to be extended in the second direction so as to be coupled to the variable resistance elements arranged in the second direction.

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