The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2016

Filed:

Jun. 06, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Jan Christian Diffenderfer, Escondido, CA (US);

Yuehchun Claire Cheng, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 11/4076 (2006.01); H03L 7/08 (2006.01); G11C 7/10 (2006.01); H03L 7/081 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G11C 7/1066 (2013.01); G11C 7/1093 (2013.01); H03L 7/08 (2013.01); H03L 7/0805 (2013.01); H03L 7/0812 (2013.01);
Abstract

Systems and methods for delay control are described herein. In one embodiment, a delay system comprises a first delay circuit configured to provide a voltage bias to a second delay circuit, wherein the voltage bias controls a delay of the second delay circuit, and to update the voltage bias at an update rate. The delay system also comprises an update controller configured to adjust the update rate of the first delay circuit. For example, the update controller may adjust the update rate based on timing requirements of a memory interface incorporating the delay system. The update rate may be reduced when the timing requirements are more relaxed to reduce power, and may be increased when the timing requirements are tighter.


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