The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2016

Filed:

Nov. 30, 2012
Applicant:

Panasonic Corporation, Osaka, JP;

Inventors:

Masashi Hoshino, Osaka, JP;

Masaaki Harada, Hyogo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06T 1/20 (2006.01); G06F 9/28 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06T 1/20 (2013.01); G06F 1/3237 (2013.01); G06F 9/28 (2013.01); G06T 2200/28 (2013.01); Y02B 60/1221 (2013.01);
Abstract

This image processing circuit performs, with reduced power consumption, pipeline processing of image data. This image processing circuit has an image processing unit which performs pipeline processing of image data having N-bit pixel data. The image processing unit has a pipeline register () having upper bit flip-flop circuits (), lower-order bit flip-flop circuits (), a comparison circuit () which determines whether the input values and the output values of the upper bit flip-flop circuits () are the same, and a clock gating control circuit () which controls supply of the clock signal such that, when the aforementioned input and output values are the same, the clock signal is not supplied to the upper bit flip-flop circuits (). The pipeline register () does not have a circuit for controlling supply of the clock signal to the lower 1-bit flip-flop circuits (), and holds pixel data or calculation results during pipeline processing.


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