Parallel snoop and hazard checking with interconnect circuitry

Abstract

A system-on-chip integrated circuitry includes interconnect circuitry for connecting transaction sources with transaction destinations. A buffer circuit buffers a plurality of access transactions received from the transaction sources before they are passed on to respective transaction destinations. Hazard checking circuitry, such as identifier reuse circuitry, performs hazard checks for access transactions in parallel with snoop operations performed by snoop circuitry for managing coherence between data values stored within the plurality of cache memories. The snoop circuitry includes snoop reordering circuitry for permitting reordering of snoop responses. The snoop circuitry may issue a snoop request for a given access transaction in parallel with the hazard checking circuitry performing one or more hazard checks for that transaction.