Programmable frequency divider providing output with reduced duty-cycle variations over a range of divide ratios

Abstract

A programmable frequency divider includes a cascade of frequency-dividing units, each capable of dividing by a first or a second factor. Each unit receives an input clock and generates a divided output clock. Each unit receives a mode control signal that specifies when to divide its input clock by the second factor if a control input allows it, otherwise dividing the input clock by the first factor. The frequency divider is designed to support a range of divide ratios that requires one or more of the units to be non-operative or unused in some intervals. The final divided clock is generated using the mode control signal of the lowest unit in the cascade and the mode control signal of the highest unit that is never set to be non-operative or unused in supporting the range. As a result, duty-cycle variations of the final divided clock are minimized.