The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2016

Filed:

Oct. 30, 2012
Applicant:

St-ericsson SA, Plan-les-Ouates, CH;

Inventors:

Carlo Crippa, Merate, IT;

Rossella Bassoli, Monza, IT;

Assignee:

ST-Ericsson SA, Plan-les-Ouates, CH;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/38 (2006.01); H03F 3/185 (2006.01); H03F 3/217 (2006.01); H03K 7/08 (2006.01);
U.S. Cl.
CPC ...
H03F 3/185 (2013.01); H03F 3/2175 (2013.01); H03K 7/08 (2013.01); H03F 2200/351 (2013.01); H03F 2200/78 (2013.01); H03F 2203/21112 (2013.01); H03F 2203/21196 (2013.01);
Abstract

A digital class D amplifier () is disclosed, comprising a pulse width modulator (PW Mod) comprising: a digital loop filter (Loop F) adapted to receive an input signal (x[n]) and a feedback signal (fb[n]), the digital loop filter (Loop_F) being adapted to process at a clock frequency (f_s) said input and feedback signals for providing as output a filtered digital signal (w[n]); a PWM conversion module (PW_CM) having an input () for receiving the filtered digital signal (w[n]) and having a first output () connected to the digital loop filter (Loop F), the PWM conversion module being adapted for processing the filtered digital signal (w[n]) and providing at said first output () the feedback signal (fb[n]). The PWM conversion module (PW_CM) comprises: a first comparator (CMP_N) adapted to compare the filtered digital signal (w[n]) with a first reference triangular waveform (VTn[n]) for providing as output a first PWM signal (yn[n]), the first reference triangular waveform having a frequency (f_osc) much lower than said clock frequency (f.s); a second comparator (CMP_P) adapted to compare the filtered digital signal (w[n]) with a second reference triangular waveform (VTp[n]) for providing as output a second PWM signal (yp[n]), the second reference triangular waveform (VTp[n]) being the inverse of the first triangular waveform (VTn[n]), said first (yn[n]) and second (yp[n]) PWM signals representing a differential output pulse width modulated signal (yn[n],yp[n]).


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