Temperature compensation method for high-density floating-gate memory

Abstract

A temperature compensation technique is provided for a non-volatile memory arrangement. The memory arrangement includes: a memory circuit () having a floating gate transistor (P) operating in weak-inversion mode and a varactor (C) with a terminal electrically coupled to a gate node of the floating gate transistor; a first current reference circuit () having a floating gate transistor (PI); a second current reference circuit () having a floating gate transistor (P); and a control module () configured to selectively receive a reference current (I, I) from a drain of the floating gate transistor in each of the first and second current reference circuits. The control module operates to determine a ratio between the reference currents received from the first and second current reference circuits, generate a tuning voltage (V) in accordance with the ratio between the reference currents and apply the tuning voltage to the varactor in the memory circuit.