The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2016

Filed:

Nov. 27, 2012
Applicant:

Board of Trustees of Michigan State University, East Lansing, MI (US);

Inventors:

Shantanu Chakrabartty, Williamston, MI (US);

Ming Gu, Lansing, MI (US);

Chenling Huang, East Lansing, MI (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 27/115 (2006.01); G11C 7/04 (2006.01); G11C 16/04 (2006.01); G11C 27/00 (2006.01); G11C 27/02 (2006.01); H01L 27/06 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11526 (2013.01); G11C 7/04 (2013.01); G11C 16/0408 (2013.01); G11C 16/0441 (2013.01); G11C 27/005 (2013.01); G11C 27/028 (2013.01); H01L 27/0629 (2013.01); H01L 28/40 (2013.01);
Abstract

A temperature compensation technique is provided for a non-volatile memory arrangement. The memory arrangement includes: a memory circuit () having a floating gate transistor (P) operating in weak-inversion mode and a varactor (C) with a terminal electrically coupled to a gate node of the floating gate transistor; a first current reference circuit () having a floating gate transistor (PI); a second current reference circuit () having a floating gate transistor (P); and a control module () configured to selectively receive a reference current (I, I) from a drain of the floating gate transistor in each of the first and second current reference circuits. The control module operates to determine a ratio between the reference currents received from the first and second current reference circuits, generate a tuning voltage (V) in accordance with the ratio between the reference currents and apply the tuning voltage to the varactor in the memory circuit.


Find Patent Forward Citations

Loading…