The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2016

Filed:

Oct. 20, 2014
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventor:

Atsuko Kawasaki, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/44 (2006.01); H01L 21/76 (2006.01); H01L 21/302 (2006.01); H01L 21/461 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/24 (2013.01); H01L 24/19 (2013.01); H01L 24/82 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/24146 (2013.01); H01L 2224/821 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06527 (2013.01);
Abstract

Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer.


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