The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2016

Filed:

Mar. 03, 2015
Applicant:

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Inventors:

Stéphane Zoll, Froges, FR;

Philippe Garnier, Meylan, FR;

Olivier Gourhant, Goncelin, FR;

Vincent Joseph, Grenoble, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3205 (2006.01); H01L 21/8234 (2006.01); H01L 29/49 (2006.01); H01L 21/324 (2006.01); H01L 21/033 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823437 (2013.01); H01L 21/0332 (2013.01); H01L 21/28088 (2013.01); H01L 21/324 (2013.01); H01L 29/4966 (2013.01);
Abstract

A method is for forming at least two different gates metal regions of at least two MOS transistors. The method may include forming a metal layer on a gate dielectric layer; and forming a metal hard mask on the metal layer, with the hard mask having a composition different from that of the metal layer and covering a first region of the metal layer and leaving open a second region of the metal layer. The method may also include diffusion annealing the intermediate structure obtained in the prior steps such as to make the metal atoms of the hard mask diffuse into the first region, and removal of the hard mask.


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