The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2016

Filed:

Sep. 29, 2014
Applicants:

Kai Yun Yow, Petaling Jaya, MY;

Chee Seng Foong, Sg. Buloh, MY;

Lan Chu Tan, Singapore, SG;

Inventors:

Kai Yun Yow, Petaling Jaya, MY;

Chee Seng Foong, Sg. Buloh, MY;

Lan Chu Tan, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/544 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 21/561 (2013.01); H01L 23/544 (2013.01); H01L 24/11 (2013.01); H01L 24/85 (2013.01); H01L 24/97 (2013.01); H01L 23/3128 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54453 (2013.01); H01L 2223/54486 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/49171 (2013.01); H01L 2924/181 (2013.01);
Abstract

A method of assembling semiconductor devices with semiconductor dies of alternative different configurations uses the same substrate panel. The dies of the selected configuration are placed in an array, mounted, and connected to internal electrical contact pads on a first face of the panel using main fiducial markings and an array of subsidiary fiducial markings corresponding universally to arrays of semiconductor dies of the different alternative configurations. The pitch of the subsidiary fiducial markings is equal to the spacing between adjacent rows of the internal electrical contact pads on the panel and is a sub-multiple of the pitch of the array of dies.


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