The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2016

Filed:

Jun. 04, 2015
Applicant:

Fuji Electric Co., Ltd., Kawasaki-shi, JP;

Inventor:

Makoto Higashidate, Hino, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/10 (2006.01); H01L 21/48 (2006.01); H01L 23/373 (2006.01); H01L 23/36 (2006.01); H01L 23/00 (2006.01); H01L 25/07 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4871 (2013.01); H01L 23/36 (2013.01); H01L 23/3735 (2013.01); H01L 23/3736 (2013.01); H01L 24/29 (2013.01); H01L 25/072 (2013.01); H01L 2224/291 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01);
Abstract

Aspects of the invention include a semiconductor device that enables both solder-outflow prevention and inhibition of seizures coming from laser processing residues. A semiconductor device can include a semiconductor chip, a plurality of insulating substrates on each of which the semiconductor chip is fixed, a heat sink having a plurality of first grooves surrounding each one of more than one predetermined arrangement area. The plurality of insulating substrates can be arranged at each of the predetermined areas, and a plurality of second grooves surrounding the first groove, wherein the second grooves are shallower in depth than each of the first grooves, and solder filled between the insulating substrate and the arrangement area on the heat sink.


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