The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2016

Filed:

Dec. 02, 2015
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Jui-Lung Chen, Hsinchu, TW;

Wei-Ting Chen, Kaohsiung, TW;

Yu-Hsi Ke, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/419 (2006.01); G11C 11/418 (2006.01); G11C 11/413 (2006.01); G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 11/412 (2013.01); G11C 11/413 (2013.01); G11C 11/418 (2013.01);
Abstract

A memory device is provided. The memory device includes a memory device, a plurality of word lines and bit lines, first and second decoders, and a control circuit. The memory array includes memory cells on rows and columns. Each word line is coupled to the memory cells in one row. Each bit line is coupled to the memory cells in one column. The first decoder selects one word line according to an address signal and a first control signal. The control circuit respectively generates the first control signal and the second control signal according to a first clock signal and a second clock signal. In the period during which the first decoder selects the one word line, the second decoder selects at least two bit lines according to the address signal and a second control signal. The memory device performs a read/write operation on the selected bit lines.


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