The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2016

Filed:

May. 21, 2015
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

James A. Welker, Leander, TX (US);

Joshua Siegel, Austin, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 11/4076 (2006.01); G11C 11/4096 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01); H03M 5/00 (2006.01); H03M 5/02 (2006.01); H03M 5/04 (2006.01); H04B 1/38 (2015.01); H04B 1/40 (2015.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G11C 7/1072 (2013.01); G11C 7/22 (2013.01); G11C 7/222 (2013.01); G11C 11/4096 (2013.01); H03M 5/00 (2013.01); H03M 5/02 (2013.01); H03M 5/04 (2013.01); H04B 1/38 (2013.01); H04B 1/40 (2013.01);
Abstract

An integrated circuit includes enable circuitry coupled to receive transmit data and configured to set a clock enable to a first logic state when a data value of the transmit data changes to a different logic state. The circuit also includes clock control circuitry coupled to receive the clock enable and a data rate clock and configured to provide a filtered data rate clock, wherein the data rate clock is provided as the filtered data rate clock while the clock enable is the first logic state. The circuit also includes a flip flop having a clock input coupled to receive the filtered data rate clock, a data output coupled to provide final transmit data in response to the filtered data rate clock, and an inverting data input coupled to the data output, wherein the final transmit data corresponds to a first delayed version of the transmit data.


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