The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2016

Filed:

Jun. 13, 2012
Applicants:

Shu-yi Yu, Sunnyvale, CA (US);

Ram Gummadi, San Jose, CA (US);

John H. Edmondson, Arlington, MA (US);

Inventors:

Shu-Yi Yu, Sunnyvale, CA (US);

Ram Gummadi, San Jose, CA (US);

John H. Edmondson, Arlington, MA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/16 (2006.01); G06F 12/06 (2006.01); G06F 12/10 (2016.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1668 (2013.01); G06F 12/0653 (2013.01); G06F 9/5077 (2013.01); G06F 12/10 (2013.01); G06F 12/109 (2013.01); G06F 2212/1028 (2013.01); Y02B 60/1225 (2013.01); Y02B 60/1228 (2013.01);
Abstract

Banks within a dynamic random access memory (DRAM) are managed with virtual bank managers. A DRAM controller receives a new memory access request to DRAM including a plurality of banks. If the request accesses a location in DRAM where no virtual bank manager includes parameters for the corresponding DRAM page, then a virtual bank manager is allocated to the physical bank associated with the DRAM page. The bank manager is initialized to include parameters needed by the DRAM controller to access the DRAM page. The memory access request is then processed using the parameters associated with the virtual bank manager. One advantage of the disclosed technique is that the banks of a DRAM module are controlled with fewer bank managers than in previous DRAM controller designs. As a result, less surface area on the DRAM controller circuit is dedicated to bank managers.


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