The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2016
Filed:
Jul. 26, 2013
Circuitry for a computing system, lsu arrangement and memory arrangement as well as computing system
Ziv Zamsky, Raanana, IL;
Moshe Anschel, Tel Mond, IL;
Itay Keidar, Kfar Saba, IL;
Itay S. Peled, Hagur, IL;
Doron Schupper, Rehovot, IL;
Yakov Tokar, Rishon Lezion, IL;
Ziv Zamsky, Raanana, IL;
Moshe Anschel, Tel Mond, IL;
Itay Keidar, Kfar Saba, IL;
Itay S. Peled, Hagur, IL;
Doron Schupper, Rehovot, IL;
Yakov Tokar, Rishon Lezion, IL;
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Abstract
A circuitry for a computing system comprising a first load/store unit, LSU, and a second LSU as well as a memory arrangement. The first LSU is connected to the memory arrangement via a first bus arrangement comprising a first write bus and a first read bus. The second LSU is connected to the memory arrangement via a second bus arrangement comprising a second write bus and a second read bus. The computing system is arranged to carry out a multiple load instruction to read data via the first read bus and the second read bus and/or to carry out a multiple store instruction to write data via the first write bus and the second write bus.